Method of aging transistor and display device including the transistor

ABSTRACT

A display device including pixels is provided. Each of the pixels includes a first transistor having a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, a second transistor having a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node, and a third transistor having a first gate electrode connected to the first scan line, a second gate electrode, a first electrode connected to the first node, and a second electrode connected to the third node. The second gate electrode may be in a floating state, and the third transistor may be aged to alleviate a leakage current in order to improve image generation.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No.10-2019-0047416 under 35 U.S.C. § 119, filed in the Korean IntellectualProperty Office on Apr. 23, 2019, the entire contents of which areherein incorporated by reference.

BACKGROUND 1. Field

The disclosure relates to a method of aging a transistor and a displaydevice including the transistor, and more specifically to aging such atransistor to prevent or alleviate a leakage current when the transistoris in an off state.

2. Description of the Related Art

As an information technology is developed, importance of a displaydevice, which is a connection medium between a user and information, isemphasized. In response to this, Usage of display devices such as aliquid crystal display device, an organic light emitting display device,and a plasma display device has been increasing as individual usersrequire such devices to both maintain livelihood and pursue recreationaland other informational goals.

When in use, a particular display device may be driven according tovarious driving frequencies. For example, when the display device isdriven at a drive frequency of 60 Hz, the display device may display 60image frames per second. In contrast, when the display device is drivenat a drive frequency of 30 Hz, the display device may display 30 imageframes per second.

When the display device is driven at a low frequency, each pixel isrequired to maintain information on each image frame for a relativelylong period of time. As a result, a leakage current may occur in eachpixel, such that the information on the image frame may not bemaintained. Accordingly, deterioration or a flicker of the image mayoccur.

SUMMARY

Embodiments herein provide a method of aging a transistor and a displaydevice including the transistor that prevents or alleviates a leakagecurrent when the transistor is in an off state. As a result, momentaryafterimage often resulting from the leakage current may likewise beprevented or alleviated.

A display device according to an embodiment may include pixels. Each ofthe pixels may include a first transistor having a gate electrodeconnected to a first node, a first electrode connected to a second node,and a second electrode connected to a third node, a second transistorhaving a gate electrode connected to a first scan line, a firstelectrode connected to a data line, and a second electrode connected tothe second node, and a third transistor having a first gate electrodeconnected to the first scan line, a second gate electrode, a firstelectrode connected to the first node, and a second electrode connectedto the third node.

The second gate electrode may be in a floating state.

The third transistor may include a semiconductor layer disposed betweenthe first gate electrode and the second gate electrode, and thesemiconductor layer may include a source region, a channel region, and adrain region.

The second gate electrode may be disposed to overlap at least a part ofat least one of the source region, the channel region, and the drainregion.

The third transistor may further include a gate insulating layerdisposed between the first gate electrode and the semiconductor layer,wherein the gate insulating layer has a first region adjacent to thedrain region and a second region adjacent to the source region, whereinan electron or hole density in the first region is higher than anelectron or hole density in the second region.

The second gate electrode may be disposed to overlap a portion of thesemiconductor layer other than the source region.

The first electrode of the third transistor may be connected to thedrain region, and the second electrode of the third transistor may beconnected to the source region.

The first electrode of the third transistor may be connected to thesource region, and the second electrode of the third transistor may beconnected to the drain region.

The third transistor may further include a gate insulating layerdisposed between the first gate electrode and the semiconductor layer,and wherein the gate insulating layer has a first region adjacent to thedrain region and a second region adjacent to the source region, whereinan electron or hole density in the first region is higher than anelectron or hole density in the second region.

The third transistor may include a first sub-transistor having asub-gate electrode connected to the first scan line, a first electrodeconnected to the first node, and a second electrode, and a secondsub-transistor having a sub-gate electrode connected to the first scanline, a first electrode connected to the second electrode of the firstsub-transistor, and a second electrode connected to the third node.

The sub-gate electrode of the first sub-transistor may be separate fromthe first electrode and the second electrode of the firstsub-transistor, and the sub-gate electrode of the second sub-transistormay be separate from the first electrode and the second electrode of thesecond sub-transistor.

One of the first sub-transistor and the second sub-transistor mayinclude the second gate electrode. The first sub-transistor may includea semiconductor layer positioned between the sub-gate electrode and thesecond gate electrode, the semiconductor layer may include a sourceregion, a channel region, and a drain region, the second gate electrodemay be disposed to overlap at least a part of at least one of the sourceregion, the channel region, and the drain region, and the firstsub-transistor may further include a gate insulating layer disposedbetween the sub-gate electrode and the semiconductor layer, wherein thegate insulating layer may include a first region adjacent to the drainregion and a second region adjacent to the source region, and wherein anelectron or hole density in the first region is higher than an electronor hole density in the second region.

The second gate electrode may be disposed to overlap at least a part ofthe semiconductor layer other than the source region.

At least one of the first sub-transistor and the second sub-transistormay include the second gate electrode.

The second gate electrode may be disposed to overlap at least a part ofat least one of the source region, the channel region, and the drainregion, and the second sub-transistor may further include a gateinsulating layer between the sub-gate electrode and the semiconductorlayer, wherein the gate insulating layer has a first region adjacent tothe drain region and a second region adjacent to the source region, andwherein an electron or hole density in the first region may be higherthan an electron or hole density in the second region.

The second gate electrode may be disposed to overlap a part of at leastone of the drain region, and the second gate electrode may not overlapthe source region.

The first sub-transistor and the second sub-transistor may include thesecond gate electrode.

Each of the pixels may further include a light emitting diode, and thesecond gate electrode may be connected to a cathode of the lightemitting diode.

A method of aging a transistor, which includes a first gate electrode, asecond gate electrode, and a semiconductor layer disposed between thefirst gate electrode and the second gate electrode, and including asource region doped with an acceptor, a channel region, and a drainregion doped with an acceptor, according to an embodiment, includesapplying a voltage higher than a voltage of the drain region to thefirst gate electrode, and applying a voltage lower than the voltage ofthe first gate electrode to the second gate electrode.

The second gate electrode may be disposed to overlap at least a part ofat least one of the source region, the channel region, and the drainregion.

The second gate electrode may be disposed to overlap at least a part ofat least one of the drain region, and the channel region.

A method of aging a transistor, which includes a first gate electrode, asecond gate electrode, and a semiconductor layer disposed between thefirst gate electrode and the second gate electrode, and including asource region doped with a donor, a channel region, and a drain regiondoped with a donor, according to an embodiment, includes applying avoltage lower than a voltage of the drain region to the first gateelectrode; and applying a voltage higher than the voltage of the firstgate electrode to the second gate electrode.

The second gate electrode may be disposed to overlap at least a part ofat least one of the source region, the channel region, and the drainregion.

The second gate electrode may be disposed to overlap at least a part ofat least one of the drain region and the channel region.

The method of aging the transistor and the display device including thetransistor herein may alleviate a leakage current when the transistor isin an off state.

The method of aging the transistor and the display device including thetransistor herein may alleviate a momentary afterimage.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the invention will become more apparentby describing in further detail embodiments thereof with reference tothe accompanying drawings, in which:

FIG. 1 shows a display device configuration according to an embodimentof the disclosure;

FIG. 2 shows a pixel according to an embodiment of the disclosure;

FIG. 3 shows a method of driving a pixel according to an embodiment ofthe disclosure;

FIG. 4 shows an instance of a leakage current of a pixel;

FIG. 5 shows a structure of a fourth transistor;

FIG. 6 is a diagram for comparing a leakage current of a transistorbefore and after aging;

FIG. 7 shows a pixel according to another embodiment of the disclosure;

FIG. 8 shows a structure of a third transistor according to anembodiment of the disclosure;

FIG. 9 shows a structure of the third transistor according to anotherembodiment of the disclosure;

FIGS. 10 to 13 shows a pixel according to another embodiment of thedisclosure; and

FIGS. 14 to 16 show an auxiliary power line for alleviating a momentaryafterimage.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, various embodiments of the invention will be described indetail with reference to the accompanying drawings. The invention may beembodied in many different forms and is not limited to the embodimentsdescribed herein.

In order to clearly illustrate the invention, parts not related to thedescription are omitted, and the same or similar components are denotedby the same reference numerals throughout.

Sizes and thicknesses of the respective components shown in the drawingsare arbitrarily shown for convenience of description as the invention isnot necessarily limited to those shown in the drawings.

In the specification, the term “and/or” includes any and allcombinations of one or more of the associated listed items. Expressionssuch as “at least one of,” when preceding a list of elements, modify theentire list of elements and do not modify the individual elements of thelist. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise.

Throughout the specification, when an element is referred to as being“connected” to another element, the element may be “directly connected”to another element, or “electrically connected” to another element withone or more intervening elements interposed therebetween. It will befurther understood that when the terms “comprises,” “comprising,”“includes” and/or “including” are used in this specification, they or itmay specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of other features, integers, steps, operations, elements,components, and/or any combination thereof.

The terms “overlap” or “overlapped” means that a first object may beabove or below a second object, and vice versa.

It will be understood that, although the terms “first,” “second,”“third,” or the like may be used herein to describe various elements,these elements should not be limited by these terms. These terms areused to distinguish one element from another element or for theconvenience of description and explanation thereof. For example, when “afirst element” is discussed in the description, it may be termed “asecond element” or “a third element,” and “a second element” and “athird element” may be termed in a similar manner without departing fromthe teachings herein.

Unless otherwise defined, all terms used herein (including technical andscientific terms) have the same meaning as commonly understood by thoseskilled in the art to which this invention pertains. It will be furtherunderstood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an ideal or excessively formal sense unlessclearly defined in the specification.

FIG. 1 is a diagram showing a display device configuration according toan embodiment of the disclosure.

Referring to FIG. 1, the display device 10 according to an embodiment ofthe disclosure may include a timing controller 11, a data driver 12, ascan driver 13, a light emission driver 14, and a pixel unit 15.

The timing controller 11 may receive grayscale values and controlsignals for each frame from an external processor. The timing controller11 may render the grayscale values so that the grayscale valuescorrespond to a specification of the display device 10. For example, theexternal processor may provide a red grayscale value, a green grayscalevalue, and a blue grayscale value for each unit dot. However, when thepixel unit 15 is a pentile structure, since adjacent unit dots sharepixels, the pixels may not correspond to the respective grayscale valueson a one-to-one basis. Thus, rendering of the grayscale values isnecessary. When the pixels correspond to the respective grayscale valueson a one-to-one basis, rendering of the grayscale values may beunnecessary. The grayscale values that are not rendered or rendered maybe provided to the data driver 12. In addition, the timing controller 11may provide control signals suitable for each of the data driver 12, thescan driver 13, the light emission driver 14, and the like, to the datadriver 12, the scan driver 13, the light emission driver 14, and thelike for frame display.

The data driver 12 may generate data voltages to be provided to datalines D1, D2, D3, and Dn using the grayscale values and the controlsignals. For example, the data driver 12 may sample the grayscale valuesusing a clock signal, and apply the data voltages corresponding to thegrayscale values to the data lines D1 to Dn in units of pixel rows(where, n may be an integer greater than zero).

The scan driver 13 may receive a clock signal, a scan start signal, andthe like from the timing controller 11 to generate scan signals to beprovided to scan lines S1, S2, S3, and Sm (where, m may be an integergreater than zero).

The scan driver 13 may sequentially provide the scan signals havingpulses of a turn-on level to the scan lines S1, S2, S3, and Sm. The scandriver 13 may include scan stages configured in a form of shiftregisters. The scan driver 13 may generate the scan signals in a mannerof sequentially transferring the scan start signal, which is a pulseform of a turn-on level, to a next scan stage under a control of theclock signal.

The light emission driver 14 may receive a clock signal, a lightemission stop start signal, and the like from the timing controller 11to generate light emission signals to be provided to light emissionlines E1, E2, E3, and Eo. For example, the light emission driver 14 maysequentially provide light emission signals having pluses of a turn-offlevel to the light emission lines E1 to Eo (where, o may be an integergreater than zero). For example, each light emission stage of the lightemission driver 14 may be configured in a form of a shift register, andmay generate the light emission signals in a manner of sequentiallytransferring the light emission stop start signal, which is a pulse formof a turn-on level, to a next light emission stage under control of theclock signal.

The pixel unit 15 includes pixels. Each pixel PXij may be connected tocorresponding data line, scan line, and light emission line. Inaddition, the pixels PXij may be connected to a first power line, asecond power line, and an auxiliary power line (where, i and j may benatural numbers). The pixel PXij may refer to a pixel where a scantransistor is connected to an i-th scan line and a j-th data line.

FIG. 2 shows a pixel according to an embodiment of the disclosure.

Referring to FIG. 2, the pixel PXij includes transistors T1, T2, T3, T4,T5, T6, and T7, a storage capacitor Cst, and a light emitting diode LD.

Hereinafter, a circuit configured of a P-type transistor will bedescribed as an example. However, those skilled in the art will be ableto design a circuit configured of an N-type transistor bydifferentiating a polarity of a voltage applied to a gate terminal.Similarly, those skilled in the art will be able to design a circuitconfigured of a combination of the P-type transistor and the N-typetransistor. The P-type transistor is collectively referred to as atransistor in which an amount of current flowing when a voltagedifference between a gate electrode and a source electrode increases ina negative direction. The N-type transistor is collectively referred toas a transistor in which an amount of current flowing when a voltagedifference between a gate electrode and a source electrode increases ina positive direction. The transistor may be configured in various formssuch as a thin film transistor (“TFT”), a field effect transistor(“FET”), and a bipolar junction transistor (“BJT”).

The first transistor T1 may have a gate electrode connected to a firstnode N1, a first electrode connected to a second node N2, and a secondelectrode connected to a third node N3. The first transistor T1 may bereferred to as a driving transistor.

The second transistor T2 may have a gate electrode connected to the i-thscan line Si, a first electrode connected to the data line Dj, and asecond electrode connected to the second node N2. The second transistorT2 may be referred to as a scan transistor.

The third transistor T3 may have a gate electrode connected to the i-thscan line Si, a first electrode connected to the first node N1, and asecond electrode connected to the third node N3. The third transistor T3may be referred to as a diode-connected transistor.

The fourth transistor T4 may have a gate electrode connected to an(i−1)-th scan line S(i−1), a first electrode connected to the first nodeN1, and a second electrode connected to an initialization line INTL. Inanother embodiment, the gate electrode of the fourth transistor T4 maybe connected to another scan line. The fourth transistor T4 may bereferred to as a gate initialization transistor.

The fifth transistor T5 may have a gate electrode connected to the i-thlight emission line Ei, a first electrode connected to a first powerline ELVDDL, and a second electrode connected to the second node N2. Thefifth transistor T5 may be referred to as a light emitting transistor.In another embodiment, the gate electrode of the fifth transistor T5 maybe connected to another light emission line.

The sixth transistor T6 may have a gate electrode connected to the i-thlight emission line Ei, a first electrode connected to the third nodeN3, and a second electrode connected to an anode of the light emittingdiode LD. The sixth transistor T6 may be referred to as a light emittingtransistor. In another embodiment, the gate electrode of the sixthtransistor T6 may be connected to another light emission line.

The seventh transistor T7 may have a gate electrode connected to thei-th scan line, a first electrode connected to the initialization lineINTL, and a second electrode connected to the anode of the lightemitting diode LD. The seventh transistor T7 may be referred to as ananode initialization transistor. In another embodiment, the gateelectrode of the seventh transistor T7 may be connected to another scanline.

A first electrode of the storage capacitor Cst may be connected to thefirst power line ELVDDL and a second electrode may be connected to thefirst node N1.

The anode of the light emitting diode LD may be connected to the secondelectrode of the sixth transistor T6 and the cathode may be connected tothe second power line ELVSSL. The light emitting diode LD may include anorganic light emitting diode, an inorganic light emitting diode, aquantum dot light emitting diode, or the like.

A first power voltage may be applied to the first power line ELVDDL, asecond power voltage may be applied to the second power line ELVSSL, andan initialization voltage may be applied to the initialization lineINTL. For example, the first power voltage may be greater than thesecond power voltage. Also, the initialization voltage may be equal toor greater than the second power voltage.

FIG. 3 is a diagram for describing a method of driving a pixel accordingto an embodiment of the disclosure.

First, a data voltage DATA(i−1)j for an (i−1)-th pixel is applied to thedata line Dj and a scan signal of a turn-on level (a low level) isapplied to the (i−1)-th scan line S(i−1).

At this time, since a scan signal of a turn-off level (a high level) isapplied to the i-th scan line Si, the second transistor T2 is turned offand the data voltage DATA(i−1)j is prevented from being drawn into thepixel PXij.

At this time, since the fourth transistor T4 is turned on, the firstnode N1 is connected to the initialization line INTL, and a voltage ofthe first node N1 is initialized. Since a light emission signal of aturn-off level is applied to the light emission line Ei, the transistorsT5 and T6 are turned off and light emission of a light emitting diode LDaccording to an initialization voltage is prevented.

A data voltage DATAij for the i-th pixel PXij is applied to the dataline Dj, and the scan signal of the turn-on level is applied to the i-thscan line Si. Therefore, the transistors T2, T1, and T3 are turned on,and the data line Dj and the first node N1 are electrically connected.Thus, a compensation voltage obtained by subtracting a threshold voltageof the first transistor T1 from the data voltage DATAij is applied tothe second electrode (i.e., the first node N1) of the storage capacitorCst, and the storage capacitor Cst maintains a voltage corresponding toa difference between the first power voltage and the compensationvoltage. Such a period may be referred to as a threshold voltagecompensation period.

Since the seventh transistor T7 is turned on, the anode of the lightemitting diode LD is connected to the initialization line INTL, and thelight emitting diode LD is initialized to a charge amount correspondingto a voltage difference between the initialization voltage and thesecond power voltage.

As the emission signal of the turn-on level is applied to the lightemission line Ei, the transistors T5 and T6 may be turned on. Therefore,a driving current path is formed as a path of the first power lineELVDDL, the fifth transistor T5, the first transistor T1, the sixthtransistor T6, the light emitting diode LD, and the second power lineELVSSL.

An amount of a driving current flowing through the first electrode andthe second electrode of the first transistor T1 is controlled accordingto the voltage maintained in the storage capacitor Cst. The lightemitting diode LD emits light at a luminance corresponding to the amountof the driving current. The light emitting diode LD emits the lightuntil a light emission signal of a turn-off level is applied to thelight emission line Ei.

FIG. 4 shows an instance of a leakage current of a pixel.

Ideally, when the scan signal of the turn-off level (high level) isapplied to the gate electrodes of the transistors T3 and T4, a currentflowing through the transistors T3 and T4 is required to be zero or verysmall in an amount thereof.

However, a leakage current LC1 may be generated through the thirdtransistor T3 to be turned off in a light emission period of the lightemitting diode LD. In addition, a leakage current LC2 may be generatedthrough the fourth transistor T4 to be turned off outside aninitialization period of the first node N1. As described above, when aleakage current is generated, information on an image frame may not bemaintained, and thus an imaged may be deteriorated or otherwiseexperience a flicker thereof.

FIG. 5 shows a structure of the fourth transistor.

Referring to FIG. 5, the fourth transistor T4 may include a gateelectrode GE4, a source electrode SE4, a drain electrode DE4, and asemiconductor layer ACT4. The semiconductor layer ACT4 may include asource region SA4, a channel region CA4, and a drain region DA4. Thesource electrode SE4 may be connected to the source region SA4 and thedrain electrode DE4 may be connected to the drain region DA4.

The substrate SUB may be formed of various materials such as glass,polymer, and metal. The substrate SUB may be selected from a rigidsubstrate and a flexible substrate according to an application product.When the substrate SUB is configured to include a polymer organicmaterial, the substrate SUB may be formed of polystyrene, polyvinylalcohol, polymethyl methacrylate, polyethersulfone, polyacrylate,polyetherimide, polyethylene naphthalate, polyethylene terephthalate,polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetatecellulose, cellulose acetate propionate, and the like. On the otherhand, the substrate SUB may be formed of fiber glass reinforced plastic(“FRP”).

A barrier layer BAR may be positioned on the substrate SUB. In addition,a buffer layer BUF may be positioned on the barrier layer BAR. Inaddition, the semiconductor layer ACT4 may be positioned on the bufferlayer BUF.

The barrier layer BAR and the buffer layer BUF may be layers selectivelyincluded in the semiconductor layer ACT4 to prevent diffusion ofimpurities of the substrate SUB or moisture transmission to thesemiconductor layer ACT4. The barrier layer BAR and the buffer layer BUFmay be insulating layers. For example, the barrier layer BAR and thebuffer layer BUF may be formed of silicon nitride (SiNx), silicon oxide(SiOx), silicon oxynitride (SiOxNy), or the like.

The semiconductor layer ACT4 may be formed of polysilicon, amorphoussilicon, an oxide semiconductor, an organic semiconductor, an inorganicsemiconductor, or the like. The semiconductor layer ACT4 may include asource region SA4, a channel region CA4, and a drain region DA4.

As described above, when it is assumed that the fourth transistor T4 isthe P-type transistor, each of the source region SA4 and the drainregion DA4 may be doped with an acceptor. The first electrode of thefourth transistor T4 may be the source electrode SE4, and the secondelectrode may be the drain electrode DE4.

On the other hand, when it is assumed that the fourth transistor T4 isthe N-type transistor, each of the source region SA4 and the drainregion DA4 may be doped with a donor. The first electrode of the fourthtransistor T4 may be the drain electrode DE4 and the second electrodemay be the source electrode SE4.

Hereinafter, it is assumed that the fourth transistor T4 is a P-typetransistor.

A gate insulating layer GI may be positioned on the semiconductor layerACT4. For example, the gate insulating layer GI may be formed of siliconnitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), orthe like. A region of the gate insulating layer GI adjacent to the drainregion DA4 may have an electron density higher than that of a region ofthe gate insulating layer GI adjacent to the source region SA4. Forexample, a charge trap region CTA4 may be present in the region of thegate insulating layer GI adjacent to the drain region DA4. Electronstrapped in a lattice of the gate insulating layer (GI) and fixed inposition may be held in the charge trap region CTA4.

The gate electrode GE4 may be a conductor. For example, the gateelectrode GE4 may be formed using gold (Au), silver (Ag), aluminum (Al),molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium(Nd), copper (Cu), platinum (Pt), or the like.

An insulating layer IL may be positioned on the gate electrode GE4 andthe gate insulating layer GI. For example, the insulating layer IL maybe formed of silicon nitride (SiNx), silicon oxide (SiOx), siliconoxynitride (SiOxNy), or the like.

The source electrode SE4 and the drain electrode DE4 may be positionedon the insulating layer IL. The source electrode SE4 may be connected tothe source region SA4 through a contact hole of the insulating layer ILand the gate insulating layer GI. The drain electrode DE4 may beconnected to the drain region DA4 through the contact hole of theinsulating layer IL and the gate insulating layer GI. The sourceelectrode SE4 and the drain electrode DE4 may be formed using gold (Au),silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium(Ti), nickel (Ni), neodymium (Nd), copper (Cu), platinum (Pt), or thelike.

Each of the layers and electrodes described above may be configured of asingle layer or a plurality of layers.

Hereinafter, a method of aging a transistor according to an embodimentof the disclosure will be described.

When the transistor of a display device such as a display device 10 iscontinuously used, a characteristic of the transistor may or may not berapidly changed for a certain initial period.

An aging process of a transistor may be a process for preventing achange in the characteristic of the transistor even though a user usesthe display device 10 continuously. The aging process may includeapplying stress to the transistor as the display device 10 including thetransistor is manufactured.

The method of aging the fourth transistor according to an embodiment ofthe disclosure may be performed by applying a bias voltage higher thanthat of the drain electrode DE4 to the gate electrode GE4 of the fourthtransistor T4. Therefore, electrons are trapped in the lattice of thegate insulating layer GI and thus the charge trap region CTA4 may beformed.

FIG. 6 is a diagram for comparing a leakage current of the transistorbefore and after aging.

Referring to FIG. 6, a graph of a gate-source voltage Vgs versus draincurrent Id of the transistor is shown.

Referring to a graph AFA when the aging process is performed and a graphBFA when the aging process is not performed, it may be confirmed thatthe leakage current is alleviated when the aging process is performed.

When a high level voltage is applied to the gate electrode of the P-typetransistor, it is ideal that the transistor is turned off, such that theleakage current is not generated. However, due to a gate induced drainleakage (“GIDL”) phenomenon, a leakage current may still be generatedeven though a high level voltage is applied to the gate electrode.

A main reason of the GIDL phenomenon is tunneling according to anelectric field generated between the gate electrode and the drainelectrode. Referring to FIG. 5 again, the fourth transistor T4 accordingto an embodiment of the disclosure has a structure in which an electricfield generated by the charge trap region CTA4 compensates a certainportion of the electric field between the gate electrode and the drainelectrode, and thus the GIDL phenomenon may be alleviated.

The aging process described with reference to FIGS. 5 and 6 pertainsmainly to the P-type transistor, but the aging process described hereinmay be applied similarly to the N-type transistor.

For example, the aging process may be performed by applying a biasvoltage lower than that of the drain electrode DE4 to the gate electrodeGE4 of the N-type fourth transistor T4. Therefore, holes may be trappedin the lattice of the gate insulating layer GI, and thus the charge trapregion CTA4 may be formed. Thus, the region of the gate insulating layerGI adjacent to the drain region DA4 may have a hole density higher thanthat of the region of the gate insulating layer GI adjacent to thesource region SA4.

Referring to FIG. 4, since the gate electrode of the fourth transistorT4 is connected to the (i−1)-th scan line S(i−1) and the drain electrodeof the fourth transistor T4 is connected to the initialization lineINTL, a voltage suitable for the aging process may be convenientlyapplied to the gate electrode and the drain electrode of the transistorT4.

However, a voltage may not be applied directly to the drain electrode ofthe third transistor T3, and thus it is difficult to perform aging onthe third transistor T3.

FIG. 7 shows a pixel according to another embodiment of the disclosure.

In a pixel PXij a of FIG. 7, a configuration of a third transistor T3 ais changed as compared with the pixel PXij of FIG. 2.

Referring to FIG. 7, the third transistor T3 a may include a second gateelectrode. An electrical node of the second gate electrode may bedifferent from the first gate electrode. The second gate electrode maybe connected to an auxiliary power line BMLL. The auxiliary power lineBMLL and the second gate electrode connected to the auxiliary power lineBMLL may always be in a floating state. For example, the auxiliary powerline BMLL may not be configured to be powered. In other words, when theuser uses the display device 10, the auxiliary power line BMLL may notbe powered since the aging process occurs prior to the use by the user.

According to an embodiment of the disclosure, the auxiliary power lineBMLL may therefore be used in an aging process of the third transistorT3 a. For example, in the aging process, the auxiliary power line BMLLmay be connected to auxiliary power, and after the aging process, theauxiliary power line BMLL may be disconnected from the auxiliary power.

FIG. 8 shows a structure of the third transistor according to anembodiment of the disclosure.

Referring to FIG. 8, the third transistor T3 a may include a first gateelectrode GE3, a source electrode SE3, a drain electrode DE3, and asemiconductor layer ACT3. The semiconductor layer ACT3 may include asource region SA3, a channel region CA3, and a drain region DA3. Thesource electrode SE3 may be connected to the source region SA3 and thedrain electrode DE3 may be connected to the drain region DA3.

The barrier layer BAR may be positioned on the substrate SUB.

A second gate electrode BE may be positioned on the barrier layer BAR.The second gate electrode BE may be a conductor. The second gateelectrode BE may be formed using gold (Au), silver (Ag), aluminum (Al),molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium(Nd), copper (Cu), platinum (Pt), or the like.

In the embodiment of FIG. 8, at least a part of the second gateelectrode BE may overlap the source region SA3, the channel region CA3,and the drain region DA3. For example, the second gate electrode BE mayoverlap the source region SA3, overlap the channel region CA3, andoverlap the drain region DA3.

The buffer layer BUF may be positioned on the barrier layer BAR and thesecond gate electrode BE. In addition, the semiconductor layer ACT3 maybe positioned on the buffer layer BUF. The semiconductor layer ACT3 maybe positioned between the first gate electrode GE3 and the second gateelectrode BE.

The semiconductor layer ACT3 may be formed of polysilicon, amorphoussilicon, an oxide semiconductor, an organic semiconductor, an inorganicsemiconductor, or the like. The semiconductor layer ACT3 may include thesource region SA3, the channel region CA3, and the drain region DA3.

As described above, when it is assumed that the third transistor T3 a isthe P-type transistor, each of the source region SA3 and the drainregion DA3 may be doped with an acceptor. Thus, the first electrode ofthe third transistor T3 a may be the drain electrode DE3 and the secondelectrode may be the source electrode SE3.

On the other hand, when it is assumed that the third transistor T3 a isthe N-type transistor, each of the source region SA3 and the drainregion DA3 may be doped with a donor. Thus, the first electrode of thethird transistor T3 a may be the source electrode SE3 and the secondelectrode may be the drain electrode DE3.

Hereinafter, it is assumed that the third transistor T3 a is the P-typetransistor.

The gate insulating layer GI may be positioned on the semiconductorlayer ACT3. The gate insulating layer GI may be positioned between thefirst gate electrode GE3 and the semiconductor layer ACT3.

A region of the gate insulating layer GI adjacent to the drain regionDA3 may have an electron density higher than that of a region of thegate insulating layer GI adjacent to the source region SA3. For example,a charge trap region CTA3 may be present in the region of the gateinsulating layer GI adjacent to the drain region DA3. Electrons trappedin a lattice of the gate insulating layer (GI) and fixed in position maybe held in the charge trap region CTA3.

The insulating layer IL may be positioned on the first gate electrodeGE3 and the gate insulating layer GI.

The source electrode SE3 and the drain electrode DE3 may be positionedon the insulating layer IL. The source electrode SE3 may be connected tothe source region SA3 through the contact hole of the insulating layerIL and the gate insulating layer GI. The drain electrode DE3 may beconnected to the drain region DA3 through the contact hole of theinsulating layer IL and the gate insulating layer GI.

Each of the layers and electrodes described above may be configured of asingle layer or a plurality of layers.

Hereinafter, a method of aging the third transistor T3 a according to anembodiment of the disclosure will be described.

The method of aging the third transistor T3 a according to an embodimentof the disclosure may be performed by applying a bias voltage higherthan that of the drain electrode DE3 to the first gate electrode GE3. Atthis time, a voltage lower than that of the first gate electrode GE3 maybe applied to the second gate electrode BE. That is, the above-describedauxiliary power may provide the voltage lower than that of the firstgate electrode GE3 to the second gate electrode BE through the auxiliarypower line BMLL.

According to an embodiment of the disclosure, in a situation where it isdifficult to directly apply the voltage lower than that of the firstgate electrode GE3 to the drain electrode DE3, the voltage lower thanthat of the first gate electrode GE3 may be directly applied to thesecond gate electrode BE. Therefore, an electric field between the firstgate electrode GE3 and the drain electrode DE3 is strengthened. Thus,the electrons may be effectively trapped in the lattice of the gateinsulating layer GI based on the charge trap region CTA3.

Reduction of the leakage current due to the alleviation of the GIDLphenomenon due to the charge trap region CTA3 is the same as thatdescribed with reference to FIG. 6.

As described, even though the third transistor T3 a is configured of theP-type, an aging process of the same principle may be performed for anN-type transistor that is the third transistor T3 a.

For example, when the third transistor T3 a is configured of the N type,the source region SA3 and the drain region DA3 may be doped with adonor.

The aging method according to an embodiment of the disclosure mayinclude applying a voltage lower than that of the drain region DA3 tothe first gate electrode GE3. That is, the voltage lower than that ofthe drain electrode DE3 may be applied to the first gate electrode GE3.In addition, the aging method may include applying a voltage higher thanthat of the first gate electrode GE3 to the second gate electrode BE.Therefore, holes may be trapped in the lattice of the gate insulatinglayer GI, and thus the charge trap region CTA3 may be formed. As such,the region of the gate insulation layer GI adjacent to the drain regionDA3 may have a hole density higher than that of the region of the gateinsulation (GI) layer adjacent to the source region SA3.

FIG. 9 shows a structure of the third transistor according to anotherembodiment of the disclosure.

A third transistor T3 a′ of FIG. 9 is different from the thirdtransistor T3 a of FIG. 8 with respect to a second gate electrode BE′.

At least a part of the second gate electrode BE′ may overlap the drainregion DA3. In addition, the second gate electrode BE′ may not overlapthe source region SA3.

According to the foregoing description, the charge trap region CTA3 isrequired to be formed in a portion close to the drain region DA3 of thegate insulating layer GI. Therefore, it is sufficient that an electricfield provided by the second gate electrode BE′ is provided to the drainregion DA3.

FIGS. 10 to 13 show a pixel according to another embodiment of thedisclosure.

In a pixel PXijb of FIG. 10, a configuration of a third transistor T3 bmay differ from the pixel PXija of FIG. 7. Repetitive descriptions ofthe same configuration of the pixel PXijb and the pixel PXija will beomitted.

The third transistor T3 b may include a first sub-transistor T3 b 1 anda second sub-transistor T3 b 2.

The first sub-transistor T3 b 1 may have a sub-gate electrode connectedto the i-th scan line Si, a first electrode connected to the first nodeN1, a second electrode connected to the first electrode of the secondsub-transistor T3 b 2.

The second sub-transistor T3 b 2 may have a sub-gate electrode connectedto the i-th scan line Si, a first electrode connected to the secondelectrode of the first sub-transistor T3 b 1, a second electrodeconnected to the third node N3.

Each of the sub-gate electrodes which are shown in FIG. 10 as beingconnected to the i-th scan line Si is distinct from the gate electrodeGE3, as is shown in FIG. 8, for example. That is, each sub-gateelectrode forms a separate connection of the third transistor T3 a tothe scan line Si.

The first sub-transistor T3 b 1 may include a second gate electrode. Thesecond gate electrode may be connected to the auxiliary power line BMLL.A structure of the first sub-transistor T3 b 1 may include the structureof the third transistors of FIG. 8 and FIG. 9.

However, the second sub-transistor T3 b 2 may not include the secondgate electrode. A structure of the second sub-transistor T3 b 2 mayinclude the structure of the transistor T4 of FIG. 5.

In order to prevent a leakage current, the first sub-transistor T3 b 1and the second sub-transistor T3 b 2 may be connected in series. Sincethe first sub-transistor T3 b 1 and the second sub-transistor T3 b 2connected in series share the same current path, the aging process maybe performed only on the first sub-transistor T3 b 1 to alleviate theleakage current.

In a pixel PXijb′ of FIG. 11, a configuration of a third transistor T3b′ may differ from the pixel PXija of FIG. 7.

The third transistor T3 b′ may include a first sub-transistor T3 b 1′and a second sub-transistor T3 b 2′.

The first sub-transistor T3 b 1′ may have a sub-gate electrode connectedto the i-th scan line Si, a first electrode connected to the first nodeN1, a second electrode connected to the first electrode of the secondsub-transistor T3 b 2′.

The second sub-transistor T3 b 2′ may have a sub-gate electrodeconnected to the i-th scan line Si, a first electrode connected to thesecond electrode of the first sub-transistor T3 b 1′, and a secondelectrode connected to the third node N3.

At this time, the first sub-transistor T3 b 1′ may not include thesecond gate electrode. A structure of the first sub-transistor T3 b 1′may include the structure of the transistor T4 of FIG. 5.

However, the second sub-transistor T3 b 2′ may include the second gateelectrode. The second gate electrode may be connected to the auxiliarypower line BMLL. A structure of the second sub-transistor T3 b 2′ mayfollow the structure of the transistors of FIG. 8 and FIG. 9.

In order to prevent a leakage current, the first sub-transistor T3 b 1′and the second sub-transistor T3 b 2′ may be connected in series. Sincethe first sub-transistor T3 b 1′ and the second sub-transistor T3 b 2′connected in series share the same current path, the aging process maybe performed only on the second sub-transistor T3 b 2′ to alleviate theleakage current.

In a pixel PXijb″ of FIG. 12, a configuration of a third transistor T3b″ may differ from the pixel PXija of FIG. 7.

The third transistor T3 b″ may include a first sub-transistor T3 b 1″and a second sub-transistor T3 b 2″.

The first sub-transistor T3 b 1″ may have a sub-gate electrode connectedto the i-th scan line Si, a first electrode connected to the first nodeN1, and a second electrode connected to the first electrode of thesecond sub-transistor T3 b 2″.

The second sub-transistor T3 b 2″ may have a sub-gate electrodeconnected to the i-th scan line Si, a first electrode connected to thesecond electrode of the first sub-transistor T3 b 1″, and a secondelectrode connected to the third node N3.

The first sub-transistor T3 b 1″ and the second sub-transistor T3 b 2″may include a second gate electrode. The second gate electrode may beconnected to the auxiliary power line BMLL. Structures of the firstsub-transistor T3 b 1″ and the second sub-transistor T3 b 2″ may followthe structure of the transistors of FIG. 8 and FIG. 9.

In a pixel PXijc of FIG. 13, configurations of a third transistor T3 cand a fourth transistor T4 c may differ from the pixel PXija of FIG. 7.

The third transistor T3 c may include a first sub-transistor T3 c 1 anda second sub-transistor T3 c 2.

The first sub-transistor T3 c 1 may have a sub-gate electrode connectedto the i-th scan line Si, a first electrode connected to the first nodeN1, a second electrode connected to the first electrode of the secondsub-transistor T3 c 2.

The second sub-transistor T3 c 2 may have a sub-gate electrode connectedto the i-th scan line Si, a first electrode connected to the secondelectrode of the first sub-transistor T3 c 1, a second electrodeconnected to the third node N3.

The first sub-transistor T3 c 1 and the second sub-transistor T3 c 2 mayinclude a second gate electrode. The second gate electrode may beconnected to the auxiliary power line BMLL. Structures of the firstsub-transistor T3 c 1 and the second sub-transistor T3 c 2 may followthe structure of the transistors of FIG. 8 and FIG. 9.

The pixel PXijc of FIG. 13 includes sub-transistors T4 c 1 and T4 c 2 inwhich the fourth transistors T4 c are connected in series in order toreduce the leakage current LC2 described above with reference to FIG. 4.

The sub-transistor T4 c 1 may have a gate electrode connected to the(i−1)-th scan line S(i−1), a first electrode connected to the first node(N1), and a second electrode connected to a first electrode of thesub-transistor T4 c 2.

The sub-transistor T4 c 2 may have a gate electrode connected to the(i−1)-th scan line S(i−1), the first electrode connected to the secondelectrode of the sub-transistor T4 c 1, and a second electrode connectedto the initialization line INTL.

Each of the sub-transistors T4 c 1 and T4 c 2 may follow the structureof the transistor T4 of FIG. 5.

FIGS. 14 to 16 show an auxiliary power line for alleviating a momentaryafterimage.

The above-described embodiments are applicable even though the auxiliarypower line BMLL of the display device 10 is always maintained in thefloating state.

However, in the embodiments of FIGS. 14 to 16, momentary afterimage maybe alleviated by configuring the auxiliary power line BMLL to receivepower after the driving the display device 10 has been manufactured andis readied for delivery to a user. That is, in the embodiments of FIGS.14 to 16, the auxiliary power line BMLL may not always be maintained inthe floating state.

A hysteresis characteristic may arise when, with respect to thegate-source voltage versus drain current curve of the first transistorT1, a data voltage of a current image frame is higher than a datavoltage of a previous image frame and the data voltage of the currentimage frame is lower than the data voltage of the previous image frame.Therefore, when the hysteresis characteristic appears strongly in aninstance in which the same gate-source voltage is applied, the amount ofthe driving current flowing through the first transistor T1 may vary soas to cause the light emitting diode LD to not emit light at anappropriate luminance corresponding to the grayscale value.

When the display device 10 displays a still image, the first transistorsof the pixels receive the same gate-source voltage during several tensto several hundreds of image frame periods. Therefore, when thehysteresis characteristics of the first transistors are maximized in thestill image and the display device 10 switches the image, the pixels maynot emit light appropriately at the luminance corresponding to thegrayscale value. When afterimage persists, continuance of the same maybe regarded as momentary afterimage. Such momentary afterimage may lastfor a few seconds and be perceived by the user of a display device forthat corresponding amount of time.

In order to address and prevent such a momentary afterimage, a number oftechniques may be implemented. For example and with respect to theembodiments of FIGS. 14 to 16, an absolute value of a threshold voltageof the third transistor may be reduced by applying a voltage lower thanthat of the first gate electrode to the second gate electrode of thethird transistor. Therefore, a switching speed of the third transistoris increased to advance a turn-on time of the third transistor, therebyalleviating the degree and/or existence of momentary afterimage.

Referring to FIG. 14, the auxiliary power line BMLL and the second powerline ELVSSL may be connected through a switch SW.

The switch SW may be turned off at the time of the aging of the displaydevice 10. Therefore, an appropriate voltage for the aging may beapplied to the auxiliary power line BMLL. In another embodiment, theswitch SW may be turned on when it is appropriate to apply the secondpower voltage to the auxiliary power line BMLL at the time of the agingof the display device 10.

The switch SW may also be turned on at the time of driving the displaydevice 10. Therefore, the second power line ELVSSL may be connected tothe auxiliary power line BMLL. Generally, since the second power voltageof the voltages applied to the pixel is the lowest voltage, a voltagelower than that of the first gate electrode may be applied to the secondgate electrode of the third transistor. According to an embodiment, atthe time of driving the display device 10, the switch SW may not alwaysturned on, but a timing thereof may be appropriately set to address themomentary afterimage.

Referring to FIG. 15, the auxiliary power line BMLL and the second powerline ELVSSL may be directly connected with each other. That is, thesecond gate electrode may be connected to the cathode of the lightemitting diode LD (see FIG. 7).

Therefore, the second power voltage lower than that of the first gateelectrode may be applied to the second gate electrode both at the timeof the aging process and at the time of the driving of the displaydevice 10. Therefore, the leakage current alleviation and the momentaryafterimage alleviation may be simultaneously achieved.

Referring to FIG. 16, an auxiliary power supply APP may be connected tothe auxiliary power line BMLL and a second power supply PP2 may beconnected to the second power line ELVSSL.

The auxiliary power supply APP may provide a voltage corresponding tothe above-described embodiments to the auxiliary power line BMLL at thetime of the aging process and at the time of the driving.

The second power supply PP2 may provide the second power voltagecorresponding to the above-described embodiments to the second powerline ELVSSL at the time of the aging process and at the time of thedriving.

In the embodiment of FIG. 16, the auxiliary power line BMLL and thesecond power line ELVSSL are separated from each other, and thus avoltage control may be easily performed.

In FIGS. 14 to 16, it is assumed that the third transistor is configuredof the P-type transistor.

In another embodiment, when the third transistor is configured of theN-type transistor, in the embodiments of FIGS. 14 to 16, the absolutevalue of the threshold voltage may be reduced by applying a voltagehigher than that of the first gate electrode to the second gateelectrode of the third transistor.

Thus, the second power line ELVSSL of FIGS. 14 to 16 may be replacedwith the first power line ELVDDL. In addition, the second power supplyPP2 of FIG. 16 may be replaced with the first power supply.

The aforementioned description is provided to exemplify and describe theinvention. In addition, the aforementioned description simplyexemplifies and describes embodiments of the disclosure, may be appliedto various other combinations, modifications, and environments as setforth above, and may be changed or modified within the scope of theinvention.

What is claimed is:
 1. A display device comprising: pixels; wherein eachof the pixels comprises: a first transistor having a gate electrodedirectly electrically connected to a first node, a first electrodedirectly electrically connected to a second node, and a second electrodedirectly electrically connected to a third node; a second transistorhaving a gate electrode connected to a first scan line, a firstelectrode connected to a data line, and a second electrode directlyelectrically connected to the second node; and a third transistor havinga first gate electrode connected to the first scan line, a second gateelectrode, a first electrode directly electrically connected to thefirst node, and a second electrode directly electrically connected tothe third node.
 2. The display device according to claim 1, wherein thesecond gate electrode is in a floating state.
 3. The display deviceaccording to claim 1, wherein the third transistor comprises asemiconductor layer disposed between the first gate electrode and thesecond gate electrode, and the semiconductor layer includes a sourceregion, a channel region, and a drain region.
 4. The display deviceaccording to claim 3, wherein the second gate electrode is disposed tooverlap at least a part of at least one of the source region, thechannel region, and the drain region.
 5. The display device according toclaim 4, wherein the third transistor further comprises a gateinsulating layer disposed between the first gate electrode and thesemiconductor layer, wherein the gate insulating layer has a firstregion adjacent to the drain region and a second region adjacent to thesource region, wherein an electron or hole density in the first regionis higher than an electron or hole density in the second region.
 6. Thedisplay device according to claim 3, wherein the second gate electrodeis disposed to overlap a portion of the semiconductor layer other thanthe source region thereof.
 7. The display device according to claim 6,wherein the first electrode of the third transistor is connected to thedrain region, and the second electrode of the third transistor isconnected to the source region.
 8. The display device according to claim6, wherein the first electrode of the third transistor is connected tothe source region, and the second electrode of the third transistor isconnected to the drain region.
 9. The display device according to claim6, wherein the third transistor further comprises a gate insulatinglayer disposed between the first gate electrode and the semiconductorlayer, and wherein the gate insulating layer has a first region adjacentto the drain region and a second region adjacent to the source region,wherein an electron or hole density in the first region is higher thanan electron or hole density in the second region.
 10. The display deviceaccording to claim 1, wherein the third transistor comprises: a firstsub-transistor having a sub-gate electrode connected to the first scanline, a first electrode connected to the first node, and a secondelectrode; and a second sub-transistor having a sub-gate electrodeconnected to the first scan line, a first electrode connected to thesecond electrode of the first sub-transistor, and a second electrodeconnected to the third node.
 11. The display device according to claim10, wherein the sub-gate electrode of the first sub-transistor isseparate from the first electrode and the second electrode of the firstsub-transistor, and the sub-gate electrode of the second sub-transistoris separate from the first electrode and the second electrode of thesecond sub-transistor.
 12. The display device according to claim 10,wherein one of the first sub-transistor and the second sub-transistorincludes the second gate electrode.
 13. The display device according toclaim 12, wherein the first sub-transistor comprises a semiconductorlayer disposed between the sub-gate electrode and the second gateelectrode, the semiconductor layer includes a source region, a channelregion, and a drain region, the second gate electrode is disposed tooverlap at least a part of at least one of the source region, thechannel region, and the drain region, the first sub-transistor furthercomprises a gate insulating layer between the sub-gate electrode and thesemiconductor layer, wherein the gate insulating layer has a firstregion adjacent to the drain region and a second region adjacent to thesource region, and wherein an electron or hole density in the firstregion is higher than an electron or hole density in the second region.14. The display device according to claim 12, wherein the second gateelectrode is disposed to overlap at least a part of the semiconductorlayer other than the source region.
 15. A display device comprising:pixels, wherein each of the pixels comprises: a first transistor havinga gate electrode connected to a first node, a first electrode connectedto a second node, and a second electrode connected to a third node; asecond transistor having a gate electrode connected to a first scanline, a first electrode connected to a data line, and a second electrodeconnected to the second node; and a third transistor having a first gateelectrode connected to the first scan line, a second gate electrode, afirst electrode connected to the first node, and a second electrodeconnected to the third node, wherein the third transistor comprises: afirst sub-transistor having a sub-gate electrode connected to the firstscan line, a first electrode connected to the first node, and a secondelectrode; and a second sub-transistor having a sub-gate electrodeconnected to the first scan line, a first electrode connected to thesecond electrode of the first sub-transistor, and a second electrodeconnected to the third node, and at least one of the firstsub-transistor and the second sub-transistor includes the second gateelectrode.
 16. The display device according to claim 15, wherein thesecond sub-transistor comprises a semiconductor layer disposed betweenthe sub-gate electrode and the second gate electrode, the semiconductorlayer includes a source region, a channel region, and a drain region,the second gate electrode overlaps at least a part of at least one ofthe source region, the channel region, and the drain region, and thesecond sub-transistor further comprises a gate insulating layer disposedbetween the sub-gate electrode and the semiconductor layer, wherein thegate insulating layer has a first region adjacent to the drain regionand a second region adjacent to the source region, and an electron orhole density in the first region is higher than an electron or holedensity in the second region.
 17. The display device according to claim15, wherein the second gate electrode is disposed to overlap a part ofthe semiconductor layer other than the source region.
 18. The displaydevice according to claim 10, wherein the first sub-transistor and thesecond sub-transistor comprise the second gate electrode.
 19. Thedisplay device according to claim 1, wherein each of the pixels furthercomprises a light emitting diode, and the second gate electrode isconnected to a cathode of the light emitting diode.
 20. A method ofaging a transistor comprising a first gate electrode, a second gateelectrode, a semiconductor layer disposed between the first gateelectrode and the second gate electrode, and including a source regiondoped with an acceptor, a channel region, and a drain region doped withan acceptor, and a gate insulating layer disposed between the first gateelectrode and the semiconductor layer, the method comprising: applying avoltage higher than a voltage of the drain region to the first gateelectrode; and applying a voltage lower than the voltage of the firstgate electrode to the second gate electrode such that electrons aretrapped in a lattice of the gate insulating layer.
 21. The methodaccording to claim 20, wherein the second gate electrode overlaps atleast a part of at least one of the source region, the channel region,and the drain region.
 22. The method according to claim 20, wherein thesecond gate electrode overlaps at least a part of at least one of thedrain region and the channel region.
 23. A method of aging a transistor,comprising a first gate electrode, a second gate electrode, asemiconductor layer disposed between the first gate electrode and thesecond gate electrode, and including a source region doped with a donor,a channel region, and a drain region doped with a donor, and a gateinsulating layer disposed between the first gate electrode and thesemiconductor layer, the method comprising: applying a voltage lowerthan a voltage of the drain region to the first gate electrode; andapplying a voltage higher than the voltage of the first gate electrodeto the second gate electrode such that holes are trapped in a lattice ofthe gate insulating layer.
 24. The method according to claim 23, whereinthe second gate electrode is disposed to overlap at least a part of atleast one of the source region, the channel region, and the drainregion.
 25. The method according to claim 23, wherein the second gateelectrode is disposed to overlap at least a part of at least one of thedrain region and the channel region.